This invention relates to a method of manufacturing a semiconductor device and, in particular, to a method of manufacturing a complementary metal oxide semiconductor field effect transistor (CMOSFET) having a metal silicide film formed on at least source and drain regions.
In metal oxide semiconductor field effect transistors (MOSFETs) composing an integrated circuit (IC), miniaturization of gate electrodes has been progressing. In the MOSFETs having minute gate electrodes, parasitic resistance of the gate electrodes and the source and drain regions are relatively higher than channel resistance of the MOSFETs. As a result, such MOSFETs are disadvantageous in that a drain current decreases.
In order to prevent the above-mentioned degradation of a device characteristic, two types of MOSFETs have been already proposed. One type is an MOSFET of salicide (self-aligned silicide) structure while another type is an MOSFET of polycide structure. The MOSFET of salicide structure is an MOSFET wherein metal silicide films are simultaneously formed on the gate electrode and the source and drain regions. The MOSFET of polycide structure is an MOSFET wherein the gate electrode comprises structure of two layers which is a combination of a metal silicide film and a polysilicon film.
However, as reported by Minoru Takahashi et al. in a paper contributed to "Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials", Makuhari, 1993, pages 458-460, under the title of "Anomalous Resistance in 0.1 .mu.m-Region Ti-Silicided Poly Si Gate", the MOSFET of salicide structure is disadvantageous in that the metal silicide film on the gate electrode has high electric resistance when the gate electrode is miniaturized as will later be described in conjunction with FIGS. i(A) through i(D).
In addition, as reported by Robert Beyers et al. in a paper contributed to "JOURNAL OF APPLIED PHYSICS", Vol. 61, No. 11 (1 Jun. 1987), pages 5110-5117, under the title of "Titanium disilicide formation on heavily doped silicon substrates", silicide forming reaction depends on types of and concentration of impurities in a silicon substrate. As a result, in the manner which will later be described in conjunction with FIGS. 1(A) through 1(D) and FIGS. 2(A) through 2(D), conventional manufacturing processes for CMOSFETs are disadvantageous in that it is impossible to obtain metal silicide films on a P-channel MOSFET region and metal silicide films on an N-channel MOSFET region which have thicknesses equal to each other. This is because the silicide forming reaction is carried out after impurities are doped in the silicon substrate and the metal silicide films are simultaneously formed on the P-channel MOSFET region and the N-channel MOSFET region.
In addition, it is difficult to form metal silicide films having thick thicknesses on the source and drain regions. This is because the source and drain regions have a shallow junction depth due to better performance of a device with miniaturization of the device.
To solve this problem, "laying-on structure" are already proposed, for example, Japanese Unexamined Patent Prepublication No. 14461/1985, Japanese Unexamined Patent Prepublication No. 128656/1985, and Japanese Unexamined Patent Prepublication No. 3461/1986. However, the laying-on structure causes trouble as follows. Parasitic capacitance increases because the gate electrode and the drain region are adjacent to each other. It is difficult to form a junction depth of the source and drain regions with good control. It is difficult to form a metal silicide film because the metal silicide film is formed after diffusion of impurity in the source and drain regions.